The present invention relates to an amplification type solid-state imaging device for amplifying and extracting signals obtained by photoelectric conversion means, and especially a pixel signal readout driving circuit of CMOS type image sensor, which can be used for video cameras, electric still cameras or the like capable of electronic shutter control operation.
In recent years, the amplification type CMOS image sensor, known as solid-state imaging device appropriate for the application to video cameras, electric still cameras or the like, has a structure to amplify and extract signals obtained by the photoelectric conversion means for each cell by a MOS transistor. To be more specific, the charge detection node reads out the signal charges generated by the photoelectric conversion means, and the pixel cell itself is provided with the amplification function, by amplifying the potential of the detection node with the amplification transistor inside the pixel cell.
Such CMOS image sensor is still more expected, because it is highly sensitive and appropriate for minimization of the pixel by the increase of pixel number or reduction of the image size, in addition to its low power consumption.
FIG. 9 shows schematically a configuration of conventional 330 thousands pixel amplification type CMOS image sensor provided with a readout circuit capable of reading out a pixel signal for every one pixel.
In FIG. 9, the imaging region A includes unit cells 1 of one pixel/one unit arranged in a matrix of rows and columns. Each unit cell 1 is composed of, for instance, four transistors Ta, Tb, Tc, Td and one photodiode PD. In other words, each unit cell 1 comprises a photodiode PD that a ground potential is applied to its anode, a readout transistor (shutter gate transistor) Td whose one end is connected to the cathode of the photodiode PD, an amplifying transistor Tb whose gate is connected to the other end of the readout transistor Td, a vertical selection transistor (row selection transistor) Ta whose one end is connected to one end of the amplifying transistor Td, and a reset transistor Tc whose one end is connected to a gate of a amplifying transistor Tb.
In addition, the imaging region A comprises a readout line 4 connected in common to the gate of each readout transistor Td of the unit cell 1 in the same row, a vertical selection line 6 connected in common to the gate of each vertical selection transistor Ta of the unit cell 1 in the same row, and a reset line 7 connected in common to the gate of each reset transistor Tc of the unit cell 1 in the same row, in correspondence to each pixel row.
Further, the imaging region A includes a vertical signal line VLIN connected in common to the other end of each amplifying transistor Tb of the unit cell 1 in the same column, and a power supply line 9 connected in common to the other end of each reset transistor Tc and to the other end of respective vertical selection transistor Ta of the unit cell 1 in the same column, in correspondence to each pixel line.
Arranged in a horizontal direction in a first external region (not shown) of the imaging region A are a plurality of load transistors TL each of which is connected between each one end of the vertical signal line VLIN and the ground node to which gate a bias voltage VVL is applied.
Moreover, a plurality of noise canceller circuits composed, for instance, of two transistors TSH, TCLP and two capacitors Cc, Ct are arranged in the horizontal direction, in the second external region (not shown) of the imaging region A. And, a plurality of horizontal selection transistor TH connected to respective other end of the vertical signal line VLIN through the noise canceller circuit are arranged in the horizontal direction.
Further, a horizontal signal line HLIN is connected in common to the other end of the horizontal selection transistor TH, and a horizontal reset transistor (not shown) and an output amplification circuit AMP are connected to the horizontal signal line HLIN.
Here, the respective noise canceller circuit is comprised of a sample hold transistor TSH whose one end is connected to the other end of the vertical signal line VLIN, a coupling capacitor Cc whose one end is connected to the other end of the sample hold transistor TSH, a charge storage capacitor Ct connected between the other end of the coupling capacitor Cc and the ground node, and a potential clamp transistor TCLP whose one end is connected to the connection node of these two capacitors Cc, Ct and whose the other end is supplied with bias voltage VVC, and one end of the horizontal selection transistor TH is connected to the connection node of two capacitors Cc, Ct.
Also, arranged in a third external region (not shown) of the image region A are a vertical shift register 2 for selecting and controlling a plurality of vertical selection line 6 of the imaging region, a pulse selector 2a for driving the readout line 4 or the like of each row of the imaging region by selecting and controlling the output pulse of the vertical shift register 2, and a horizontal shift register 3 for driving the horizontal selection transistor TH.
Further, arranged in a fourth external region (not shown) of the imaging region A are a timing generation circuit 10 for generating various internal signals, based on an external input pulse signal at a predetermined timing, and supplying to the pulse selector 2a, the horizontal shift register 3, the noise canceller circuit or the like, and a bias generation circuit 11 for generating a predetermined bias potential at one end or other of the potential clamp transistor TCLP of the noise canceller circuit.
FIG. 10 is a timing waveform diagram showing an example of the operation of the solid-state image sensor shown in FIG. 9. Now, referring to FIG. 10, the operation of the solid-state image sensor shown in FIG. 9 will be described.
Signal charges generated by photoelectric conversion of incident light are stored in the photodiode PD.
In the horizontal blanking period, when the signal charges of the photodiode PD are read out from the unit cell 1 of any one row, first, each vertical signal line VLIN is selected. Next, the signal line (φADRESi) of the vertical selection line 6 of the row to be selected is selected, and a vertical selection pulse signal φADRES is applied thereto, thereby turning on the line selection transistors Ta of one row.
For the unit cell 1 of one row thus selected, a source follower circuit, comprised of the amplifying transistor Tb and the load transistor TL supplied with power supply potential VDD (for instance 3.3V) through the row selection transistor Ta, is operated.
Next, in the unit cell 1 of one row thus selected, a reset pulse signal φRESET is applied by selecting the signal line (φRESETi) of the reset line 7, and the voltage of the gate of the amplifying transistor Tb (signal detection node DN) is reset to the reference voltage for a fixed period, thereby providing the reference voltage to the vertical signal line VLIN. However, the gate potential of the amplifying transistor Tb of the unit cell 1 of one row reset here is changed, and the reset potential of the vertical signal line VLIN of its other end with become uneven.
Therefore, to compensate the unevenness of the reset potential of the vertical signal line VLIN, the driving signal (φSH pulse) of the sample hold transistor TSH in the noise canceller circuit is previously turned on. Moreover, the connection node of capacitors Cc, Ct of the noise canceller circuit is set to the reference voltage, by turning on for a predetermined time the driving signal (φCLP pulse) of the potential clamp transistor TCLP after the reference voltage is output to the vertical signal line VLIN.
Next, the readout transistor Td is turned on by turning on the signal line (φREADi) thereof by selecting the readout line 4 of a predetermined row synchronizing with the readout pulse signal φREAD, after turning off the signal line (φRESETi) of the reset line 7, and the gate potential is changed by reading out the stored charges of the photodiode PD to the gate of the amplifying transistor Tb. The amplifying transistor Tb provides a voltage signal corresponding to the change amount of the gate potential to the corresponding vertical signal line VLIN and noise canceller circuit.
Thereafter, by turning off φSH pulse in the noise canceller circuit, a signal component corresponding to the difference between the read reference voltage and the signal voltage, in other words, the signal voltage without noise is stored in the capacitor Ct for the charge storage capacitor until the corresponding horizontal selection transistor TH is turned on.
Then, by turning off the signal line (φADRESi) of the vertical selection line 6 and controlling the vertical selection transistor Ta to off state to set the unit cell to non-selected state, the imaging region and each noise canceller circuit are disconnected electrically.
During the following effective horizontal period, after the reset by the horizontal reset signal HRS from the timing generation circuit 10, the horizontal shift register 3 performs the shift operation in synchronization with the horizontal timing signal HCK. This allows to turn on sequentially the driving signal (φH pulse) of the horizontal selection transistor TH and turn on the horizontal selection transistor TH sequentially.
In this way, the signal voltage of the connection node (signal conservation node) of the capacitors Cc, Ct in the noise canceller circuit is read out sequentially on the horizontal signal line HLIN, amplified and output by the output amplification circuit AMP. Here, the aforementioned noise elimination operation is performed for each readout operation by one horizontal line.
FIG. 11 is a timing waveform diagram showing an example of operation of the timing generation circuit 10 and the vertical shift register 2 in FIG. 10. Here, a case where the CMOS image sensor of FIG. 9 is used by VGA (Video Graphic Array) system of one field (frame)=1/30 Hz is shown.
Pulse signal φHP of 15.7 KHZ and clock signal φCK of 24 MHz input from outside are shaped by a buffer circuit (not shown) and are input to the timing generation circuit 10. Pulse signal φVR of 30 KHZ and pulse signal φHP of 15.7 KHZ input from outside are shaped by a buffer circuit (not shown) and are input to the vertical shift register 2.
The vertical shift register 2 clears completely the register output during “L” level period of the input pulse signal φVR and sets to “L” level, then performs the shift operation by the pulse signal φHP to set the output pulse signal ROi (i=. . . , n, n+1, . . . ) to “H” level sequentially and the output pulse signal ROi is applied to the pulse selector 2a. 
The pulse selector 2a selects the signal line (φADRESi) of the vertical selection line 6, the signal line (φRESETi) of the reset line 7 and the signal line (φREADi) of the readout line 4 for each selected row, and scans the selected row.
As mentioned above, the CMOS image sensor of FIG. 9 provides only once the respective output pulse signal ROi of the vertical shift register 2 for selecting and controlling a specific selected row within one field period. Namely, as the photodiode PD discharges the stored charges only one by one field, it is impossible to perform an electronic shutter operation for controlling the exposure time by controlling the signal storage time in the photodiode PD.
However, in general, solid-state imaging devices such as COMS image sensor are often used under various external light such as, indoor or in open air, or further, daytime or night time. Therefore, the electronic shutter operation for adjusting the exposure time and, consequently, setting the sensitivity to the optimal value by controlling the charge storage period in the photodiode according to the variation of external light or the like, is often required.
Therefore, in addition to the vertical shift register 2 for providing the output pulse signal ROi, if a vertical shift register for the electronic shutter for selecting and controlling each pixel row prior to the vertical shift register 2 is provided to the aforementioned CMOS image sensor of FIG. 9, the photodiode signal storage time of each pixel row can be controlled based on respective output pulse signals from these two vertical shift registers, allowing, as a result, to perform the electronic shutter operation.
Now, a configuration of an amplification type CMOS image sensor capable of electronic shutter operation will be shown schematically in FIG. 12 and, the operation waveform of the vertical shift register in FIG. 12 will be shown in FIG. 13.
In FIG. 12, the pulse signal φES of 30 KHZ and the pulse signal φHP of 15.7 KHZ input from outside are shaped respectively by a buffer circuit (not shown) and applied to the vertical shift register 20 for the electronic shutter at both the field period and the horizontal period. This vertical shift register 20 for the electronic shutter clears completely the register output during “L” level period of the input pulse signal φES and sets to “L” level, then performs the shift operation by the pulse signal φHP to set the output pulse signal ESi (i=. . . , n, n+1, . . . ) to “H” level sequentially and input to the pulse selector 2a. 
The pulse selector 2a scans the pixel row of the signal line (φRESETi) of the imaging region so as to select the reset line 7 and the signal line (φREADi) of the readout line 4 for the pixel row where the output pulse signals ROi, ESi from two vertical shift registers 2, 20 are of “H” level. In this case, for the signal line (φADRESi) of the vertical selection line 6, only the row to be selected where the output pulse signal ROi from the readout vertical shift register 2 is “H” level is selected and scanned.
Thus, as shown in FIG. 13, the signal line (φREADi) of the readout line 4 in each pixel row is turned on twice within one field period by two vertical shift registers 2, 20. Namely, as the signal storage timing and the signal readout timing can be set in correspondence respectively to the output pulse signals ROi, ESi from the vertical shift register 20 for the electronic shutter and the readout vertical shift register 2, consequently, the electronic shutter operation for controlling the charge storage time in the photodiode can be obtained.
As mentioned above, in the CMOS image sensor shown in FIG. 12, a readout driving signal is output from the pulse selector 2a to the readout line 4 in synchronization with the readout pulse signal φREAD supplied from the timing generation circuit 10, for either of signal storage timing or signal readout timing. This allows to perform the electronic shutter operation for controlling the charge storage time in the photodiode by 1H unit.
On the other hand, it is highly expected that the CMOS image sensor be used in an environment where incident light amount is extremely abundant such as daytime outdoor, and it is required to obtain always a good image without risk of clipping of the high brightness side even under such environment. For this sake, it is desirable to realize a rapid electronic shutter operation reducing the charge storage time of the photodiode to less than 1H.
Considering such situation, the Applicant has proposed a solid-state imaging device (Japan Patent Application No. 11-286469) capable of controlling the minimum charge storage time of the photodiode to less than 1H and performing an extremely high speed electronic shutter operation.
By the way, the aforementioned CMOS image sensor shown in FIG. 9 or FIG. 12 has a problem of low dynamic range that a person by the window photographed from indoor is imaged dark, and when the sensitivity is focused to the person, the scenery of the window will become white and can not be reproduced. Moreover, as the dynamic range is determined by the signal charge amount stored in an unit cell, the capacity of the signal storage portion will be lowered to reduce the saturated signal amount and the dynamic range when the pixel cell size is reduced or the driving voltage is lowered. This low dynamic range will prevent from imaging from the small signal to large signal area.
The Applicant has already proposed a technique for resolving the problem of such low dynamic range (Japan Patent Application No. 10-185121). The technique according to the proposal is that a part of the amount of charges, read out at the signal detection node produced by the photodiode for a certain period, is removed to limit the charges at the signal detection node and that charges produced by the photodiode after this period are read out to add them to the charges stored at the signal detection node. However, it is desired that a system for increasing the dynamic range suitable for the readout driving control in the amplification type CMOS image sensor.